使用Verilog语句 ， 如何使一个双优先编码器能在8个请求输入中找出第二高优先级的确认信号

Verilog和VHDL的市场份额各占一半。我用只会用VHDL解决这个问题：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity priority2 is
port(
R: in STD_LOGIC_VECTOR(0 to 7);
A,B: out STD_LOGIC_VECTOR(2 downto 0);
E1,E2: buffer STD_LOGIC
);
end priority2;

architecture priority2_arch of priority2 is
begin
process(R,E1,E2)
begin
A <="000";B <="000";E1 <='0';E2 <='0';
for i in 0 to 7 loop
if R(i)= '1' and E1= '0' then
A <=CONV_STD_LOGIC_VECTOR(i,3);E1 <='1';
elsif R(i)='1'and E2='0' then
B <=CONV_STD_LOGIC_VECTOR(I,3);E2 <='1';
end if;
end loop;
end process;
end priority2_arch;
希望可以帮助到你。